1. Field of the Invention
The present invention is directed to a multiple stage cascaded complementary phase code compressor and, more particularly, to a compressor which uses increasing amounts of delay in each stage along with bidirectional crossover arithmetic combinations to reduce the number of stages and the number of operations required in the compression operation.
2. Description of the Related Art
Pulse compression is commonly used in radar systems to effect an increased average transmit power while retaining the desired fine range resolution in, for example, weather radar. The peak power requirement of the transmitter device is reduced as a result of pulse compression performed by a radar receiver. The long modulated radar pulses are particularly compatible with new solid-state transmitters which are inherently capable of long duty-cycle waveforms.
Many different frequency and phase coded waveforms have been considered for radar pulse compression. The binary phase codes based on Golay's complementary series, as described in M. Golay, "Complementary Series," IRE Trans. Information Theory, April 1961, has gained much attention lately because of good sidelobe characteristics. A binary complementary code pair has the property that there is an equal number of like elements with any element spacing in the first code as the number of unlike elements with the same element spacing in the second code. When A=(a.sub.1, a.sub.2, . . . ,a.sub.N) and B=(b.sub.1, b.sub.2, . . . ,b.sub.N) are complementary code pairs of N elements, the autocorrelation of the two codes is: ##EQU1## Because the property of complementary codes: EQU c.sub.0 +d.sub.0 =2N (3) EQU c.sub.j +d.sub.j =0, for j.noteq.0 (4)
That is, the combination of the two autocorrelation functions will produce a range response with zero sidelobes.
The direct pulse compressor of an N-element complementary code, which is the autocorrelation process, requires N processing elements 10-16 as shown in FIG. 1. Each of the processing elements 10-16 consists of a delay unit 18 providing a delay of duration T for each range cell or sample which is implemented with, for example, a shift register, along with an adder/subtracter unit 20 performing the complex addition or subtraction of two inputs depending on the actual phase of the code element. The processing requirement of a direct pulse compressor is very significant for large pulse compression ratios. For instance, at a Pulse Repetition Frequency (PRF) of 2 KHz, 400 range gates and a pulse compression ratio of 1024:1, the compression throughput requirement is 820 million complex additions or subtractions per second and 1024 stages 10 as in FIG. 1 would be required.